Patent number: 9195551
Abstract: A novel ECC scheme is disclosed that offers an error protection level that is at least the same as (if not better than) that of the conventional ECC scheme without negatively impacting latency and design complexity. Embodiments of the present disclosure utilize an ECC scheme which leaves up to extra 2B for metadata storage by changing the error detection and correction process flow. The scheme adopts an early error detection mechanism, and tailors the need for subsequent error correction based on the results of the early detection.
Filed: March 29, 2012
Date of Patent: November 24, 2015
Assignee: INTEL CORPORATION
Inventors: Debaleena Das, Rajat Agarwal, C. Scott Huddleston